1. Field of the Invention
The present invention pertains to a device and method for the generation of test vectors and to a testing method for integrated circuits.
The use of present-day manufacturing technologies to increase the number of integrated circuits manufactured and, thus, to reduce their cost entails a trend towards reducing their size, often to the limits of what is technologically possible. In the manufacturing process, integrated circuits that work perfectly, as well as faulty ones, are made, and the integrated circuits that work perfectly must imperatively be separated from the faulty ones. Furthermore, it is desirable to test the circuits as early as possible. This is the case, for example, with wafers which have many circuits. Thus, the manufacturing process is pursued only for integrated circuits that have successfully undergone testing.
2. Brief Description of the Prior Art
One prior art method entails the testing of integrated circuits by applying all the possible combinations of signals to them and ascertaining that the responses given by the integrated circuits comply with the expected results. For combinational circuits, the test is then said to be complete, inasmuch as there is no memory effect internal to the circuit which would make the said circuit sequential. The length of an exhaustive test sequence increases exponentially with the number of bits of test vectors to be applied to the circuit. With modern circuits, which comprise a large number of inputs and, therefore, require long test sequences, it is generally impossible or extremely expensive to conduct an exhaustive test on an integrated circuit.
Such a test would last very long and would require an excessively large memory for the testing device.
It is also possible, in prior art methods, to reduce the number of test vectors applied to an integrated circuit.
Either the testing is restricted to test vectors which can detect a limited number of faults considered to be possible, or a sequence of pseudo-random vectors is sent with a high possibility of detecting any fault in the circuit.
The flaw in methods of the exhaustive type is that they use a large number of vectors. Furthermore, prior art methods are completely inapplicable to programmable logic arrays or circuits (hereinafter called P.L.A.).
Whereas, in combinational circuits with basic logic operators, it was possible to define a few classes of faults, both simple and general enough to offer the possibility of making models of failures (jamming at 0 or at 1 etc.) in various technologies, this is not possible for P.L.A.s.
The "jamming" of an integrated circuit equipotential element is a fault in which the value "0" is associated with this equipotential element independently of the signal present at the said equipotential element.
The jamming of an integrated circuit equipotentional connection at 1 is a fault of the said circuit in which the value "1" is associated with an equipotential element of the said integrated circuit independently of the value of the signal present.
A break is an interruption in an electrical conductor.
A short-circuit is the accidental connection of two equipotential elements of an electrical circuit.
The creation of an additional operator is the creation of an unwanted transistor or diode which was not planned when designing the integrated circuit.
This case is considered to be impossible in technologies using Schottky transistors (S.T.L.) as also in most bipolar type technologies.
In these technologies, testing a set of logic operators amounts to testing the proper functioning of each operator and each connection. However, a test of this type would not detect every possible fault in P.L.A. type circuits.
The problem of testing P.L.A.s therefore stems from the fact that it is impossible to establish general models of failures in these circuits.
The device and method according to the present invention enables the logic faults of an integrated circuit to be tested efficiently while, at the same time, it diminishes the number of test vectors needed.
In a first stage, all possible faults to be detected are determined. In a second stage, a testing sequence to detect these faults is generated; this is a test sequence which causes a sequence of false circuit responses whenever any of the faults is present.
This method is general enough for testing all logic circuits, including P.L.A.s.
Advantageously, an equivalent diagram of the circuit to be tested is made. The said equivalent diagram can be processed by a generator of test vectors of a known type. The equivalent diagram is constructed such that each possible failure of the circuit is represented, in the equivalent circuit, by one of the connections being jammed at "1". It is obvious that the equivalent diagram of the circuit to be tested, for example that of the P.L.A., performs the same logic function as the circuit replaced for the test.
The idea of the equivalent circuit diagram can be applied to any technology. However the structure of this diagram depends on the production faults envisaged. For certain faults, the physical structure of the circuit must be taken into account. This is the case, for example, with short circuits between adjacent tracks.
In one alternative embodiment of the invention, the equivalent circuit diagram has sets of hierarchically-organized cells. The basic cells of the equivalent circuit diagram use, for example, HILO simulator primitives: for example, NOT, BUF, AND, NAND, OR, NOR. An equivalent circuit diagram has the following characteristics:
It performs the same logic function as the circuit or P.L.A. to be tested; PA1 Each failure is represented by one of the wires being jammed at 1; the number of unnecessary jammings at 1 (i.e. those that represent no failure) is reduced to the minimum. PA1 There is a general standard structure by which the diagram can be easily adapted to any special circuit. PA1 The contiguity of the tracks; PA1 The relative position of the vertical connections, called VIAs, on the tracks of variables; PA1 The relative position of the diodes on the tracks of monomials; PA1 The relative position of the VIAs on the tracks of monomials; PA1 The relative position of the transistor emitters on the output tracks; PA1 The grouping of diodes in one and the same pattern; PA1 The grouping of transistors in one and the same pattern.
The use of a structure with hierarchically-organized cells, for example a structure using macrocells and basic cells, gives a regular structure of the equivalent circuit diagram. It is therefore possible to acquire it graphically or to describe the circuits directly in HILO language. The equivalent circuit diagram consists, therefore, in an assembly of cells common to all the circuits which are described once and for all. Solely the assembly of various cells depends on the particular circuit.
The determination of possible faults, through which an equivalent circuit diagram can be obtained, requires a knowledge of the physical organization of the P.L.A. and especially:
3. Summary of the Invention
The main object of the invention is a device for the generation of test vectors for integrated circuits, a device comprising communication means and at least one computer, the said communication means being used to acquire a description of a circuit, the computer being capable of taking into account possible faults in the integrated circuit, namely the jammings of its equivalent circuit diagram at one, and capable of associating a set of test vectors with these jammings at "1", with each jamming at "1" being capable of modifying at least one vector.
Another object of the invention is a method to generate test vectors for integrated circuits, a method comprising a stage in which the possible logic faults are determined and a stage in which at least one test vector per possible logic fault is generated, so that the said vector applied to the said logic circuit will give a response which will be affected by the existence of the said logic fault.